1. Field of the Invention
The present invention relates generally to power systems, and more particularly, to redundant node power systems.
2. Background Information
Conventional redundant node power systems generally use either an N+N scheme (1+1, 2+2 . . . power supplies in parallel) or an N+1 scheme (power supplies in parallel) from a single AC source. These conventional redundant power systems are expensive to implement and require extra space in the rack for accommodating the hardware of these power systems, thus reducing the maximum data processing capability of the rack. However, for systems that require 7×24 operations, this redundancy is required. Also, there is a problem that is encountered in using existing N+1 DC due to the difficulty in achieving AC redundancy. A known issue when using redundant power supplies is that a series ORing metal-oxide-semiconductor field-effect transistor (MOSFET) in each power supply, leads to additional power dissipation.
FIG. 1 shows a prior art parallel power system 100. As represented by the Figure, alternating current (AC) inlets AC1 and AC2 typically feed Power Train 1 and Power Train 2 in parallel, which are typically coupled to an ORing MOSFET and Electronic Circuit Breaker (ECB) Circuit. The ORing MOSFET and ECB circuit typically feed outputs J1 and J2. A Fan may be present to dissipate heat buildup in the system 100.
FIG. 2 shows a simplified schematic diagram of a prior art power system 200. The power system of this Figure has two power supplies 202, 204 connected in parallel via an ORing MOSFET 208, 210 in series with each power train respectively, and with electronic circuit breakers 216, 224 to power each domain respectively.
The problems associated with conventional systems lead to power dissipation problems, among other issues, and therefore it would be beneficial to have a redundant power system that could avoid the problems associated with conventional systems while still providing reliable power.